This invention relates generally to PIN photo diode image sensors. In particular, it relates to a plurality of elevated PIN diode image sensors in which the diode image sensor are physically isolated from each other by ion implantation regions.
An array of image sensors or light sensitive sensors detect the intensity of light received by the image sensors. The image sensors typically generate electronic signals that have amplitudes that are proportionate to the intensity of the light received by the image sensors. The image sensors can convert an optical image into a set of electronic signals. The electronic signals may represent intensities of colors of light received by the image sensors. The electronic signals can be conditioned and sampled to allow image processing.
Integration of the image sensors with signal processing circuitry is becoming more important because integration enables miniaturization and simplification of imaging systems. Integration of image sensors along with analog and digital signal processing circuitry allows electronic imaging systems to be low cost, compact and require low power consumption.
Historically, image sensors have predominantly been charged coupled devices (CCDs). CCDs are relatively small and can provide a high-fill factor. However, CCDs are very difficult to integrate with digital and analog circuitry. Further, CCDs dissipate large amounts of power and suffer from image smearing problems. An alternative to CCD sensors are active pixel sensors. Active pixel sensors can be fabricated using standard CMOS processes. Therefore, active pixel sensors can easily be integrated with digital and analog signal processing circuitry. Further, CMOS circuits dissipate small amounts of power.
FIG. 1 shows a cross-section of a prior art array of image sensors. This array of image sensors includes PIN diode sensors located over a substrate 10. An interconnection structure 12 electrically connects an N-layer 14 of the PIN diodes to the substrate 10. An I-layer 16 is formed over the N-layer 14. A P-layer 18 is formed over the I-layer 16. The P-layer 18, the I-layer 16 and the N-layer 14 form the array of PIN diode sensors. A first conductive via 20 electrically connects a first diode sensor to the substrate 10, and a second conductive via 22 electrically connects a second diode sensor to the substrate 10. A transparent conductive layer 24 is located over the array of diode sensors. A conductive lead 26 is connected to the transparent conductive layer 24. The conductive lead 26 is connected to a bias voltage which allows biasing of the P-layer 18 of the array of PIN diode sensors to a selected voltage potential.
A limitation of the image sensor structure of FIG. 1 is that the individual image sensors are not isolated from each other. That is, light received by a given image sensor effects neighboring image sensors because current can flow through the N-layer 14 between neighboring image sensors. Charge flows between the image sensors particularly when the light intensity of the received light varies greatly between neighboring image sensors. The P-layer 18, the I-layer 16 and the N-layer 14 are shared by neighboring image sensors. A trench 28 is formed to provide some isolation between the image sensors by increasing the resistance between the N-layers sections of neighboring image sensors.
It is desirable to have a plurality of active pixel sensors formed adjacent to a substrate in which the pixel sensors are isolated from each other to reduce coupling between the pixel sensors. It is desirable that the process required to form the isolated pixel sensor be easy to implement.
The invention includes an array of image sensors formed adjacent to a substrate. The array includes ion implantation regions located between the image sensors. The ion implantation regions provide physical isolation between image sensors. The physical isolation reduces coupling and cross-talk between the image sensors. The array of isolated image sensors can be formed by a simple fabrication process.
A first embodiment includes an image sensor array. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure.
A second embodiment is similar to the first embodiment. The amorphous silicon I-layer region of the second embodiment includes I-layer ion implantation regions that provide physical isolation between the inner layers of the image sensors. The I-layer ion implantation regions align with the electrode ion implantation regions.
A third embodiment is similar to the first embodiment. The third embodiment includes an amorphous silicon P-layer adjacent to the amorphous silicon I-layer. The amorphous silicon P-layer forms an outer layer of each of the image sensors.
A fourth embodiment is similar to the third embodiment. The amorphous silicon P-layer region of the fourth embodiment includes P-layer ion implantation regions that provide physical isolation between the outer layers of the image sensors.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.